Title

Application of ICT: A comparative analysis of power and device utilization of LDPC and Turbo encoders

Abstract/Description

Today, the exponentially emergent requirements for high performance communication systems operating in noisy environments arise the need of high data rate with error free communication. Due to this reason, design of channel encoders becomes critical and a performance metric is required to qualify encoder for optimized solution. In this paper, we present two encoding techniques i.e. Low Density Parity Check (LDPC) and Turbo encoder. These techniques are evaluated on the basis of FPGA resource utilization and power consumption. Post PAR simulation results show that Low Density Parity Check encoder is more efficient in terms of through put, resource utilization and power consumption than Turbo encoder.

Location

Room C5

Session Theme

Application of ICT

Session Type

Other

Session Chair

Dr. Arshad Siddiqi

Start Date

24-7-2011 1:00 PM

End Date

24-7-2011 1:20 PM

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Jul 24th, 1:00 PM Jul 24th, 1:20 PM

Application of ICT: A comparative analysis of power and device utilization of LDPC and Turbo encoders

Room C5

Today, the exponentially emergent requirements for high performance communication systems operating in noisy environments arise the need of high data rate with error free communication. Due to this reason, design of channel encoders becomes critical and a performance metric is required to qualify encoder for optimized solution. In this paper, we present two encoding techniques i.e. Low Density Parity Check (LDPC) and Turbo encoder. These techniques are evaluated on the basis of FPGA resource utilization and power consumption. Post PAR simulation results show that Low Density Parity Check encoder is more efficient in terms of through put, resource utilization and power consumption than Turbo encoder.