Title

Networks - I: Networks-on-Chip: challenges, trends and mechanisms for enhancements

Abstract/Description

The rate of increase of silicon capacity in integrated circuits (IC) will enable system integration of several billion transistors to reside on a single chip in the near future. Future system-on-chip (SoC) systems must therefore integrate up to several hundreds of cores within a single chip, and SoC designs will employ on-chip communication networks (NoCs) as a result. This paper discusses the problems with many current SoC systems, surveys the challenges and trends facing future SoC designs and proposes a mechanism for enhancing NoC strategies of the future by enhancing memory management and utilization techniques within an NoC.

Location

Eiffel 3

Session Theme

Networks - I

Session Type

Other

Session Chair

Dr. Javed Khan

Start Date

15-8-2009 4:25 PM

End Date

15-8-2009 4:45 PM

Share

COinS
 
Aug 15th, 4:25 PM Aug 15th, 4:45 PM

Networks - I: Networks-on-Chip: challenges, trends and mechanisms for enhancements

Eiffel 3

The rate of increase of silicon capacity in integrated circuits (IC) will enable system integration of several billion transistors to reside on a single chip in the near future. Future system-on-chip (SoC) systems must therefore integrate up to several hundreds of cores within a single chip, and SoC designs will employ on-chip communication networks (NoCs) as a result. This paper discusses the problems with many current SoC systems, surveys the challenges and trends facing future SoC designs and proposes a mechanism for enhancing NoC strategies of the future by enhancing memory management and utilization techniques within an NoC.