Abstract/Description
This paper presents a framework that utilizes Boolean difference theory to find test vectors for stuck-at-fault detection. The framework reads in structural-style Verilog models, and automatically injects single stuck-at-faults (either stuck-at-zero or stuck-at-one) into the models. The simulations are then performed to find minimal sets of test vectors. Using this setup, we conducted experiments on more than 4000 different circuits. The results show that an appreciable savings in test time and effort can be achieved using the method. The same setup can also be used for didactic purposes, specifically for digital design and test courses.
Keywords
Circuit testing, Circuit faults, System testing, Fault detection, Electrical fault detection, Hardware design languages
Location
Eiffel 3
Session Theme
Application of ICT - I
Session Type
Other
Session Chair
Dr. Ashraf Iqbal
Start Date
15-8-2009 5:55 PM
End Date
15-8-2009 6:15 PM
Recommended Citation
Beg, A., & Hasnain, S. (2009). Application of ICT - I: A framework for finding minimal test vectors for stuck-at-faults. International Conference on Information and Communication Technologies. Retrieved from https://ir.iba.edu.pk/icict/2009/2009/32
Application of ICT - I: A framework for finding minimal test vectors for stuck-at-faults
Eiffel 3
This paper presents a framework that utilizes Boolean difference theory to find test vectors for stuck-at-fault detection. The framework reads in structural-style Verilog models, and automatically injects single stuck-at-faults (either stuck-at-zero or stuck-at-one) into the models. The simulations are then performed to find minimal sets of test vectors. Using this setup, we conducted experiments on more than 4000 different circuits. The results show that an appreciable savings in test time and effort can be achieved using the method. The same setup can also be used for didactic purposes, specifically for digital design and test courses.
